Simulate half adder Using Verilog.
The addition of 2 bits is done using a combination circuit called Half adder. The input variablesare augend and addend bits and output variables are sum & carry bits. A and B are the two input bits.
Module:
This Code Should be placed in halfadder.v Named File.
module halfadder(a,b,sum,carry);
input a;
input b;
output sum;
output carry;
assign sum= (a|b);
assign carry= a&b;
endmodule
Test Bench:
This Code Should be placed in halfadder_tb.v Named File.`timescale 1ns/1ns
module halfadder_tb;
reg A;
reg B;
wire Sum;
wire Carry;
halfadder uut(A,B,Sum,Carry);
initial begin
$dumpfile("halfadder_tb.vcd");
$dumpvars(0,halfadder_tb);
A=0;B=0;
#10;
A=0;B=1;
#10;
A=1;B=0;
#10;
A=1;B=1;
$display("Test complete");
end
initial begin
$monitor("t=%3d,A=%d,B=%d,sum=%d,carry=%d",$time,A,B,Sum,Carry);
end
endmodule
Result:
