Simulate Full adder using Verilog.

Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs are A and B and the third input is an input carry as C-IN.

Module:

This Code Should be placed in fulladder.v Named File.

module fullader(x,y,cin,sum,cout);

input x;

input y;

input cin;

output sum;

output cout;

assign sum=((x^y)^cin); assign cout=((x&y)|cin); 

endmodule

Test Bench:

This Code Should be placed in fulladder_tb.v Named File.

`timescale 1ns/1ns

module fullader_tb;

reg x;

reg y;

reg cin;

wire sum;

wire cout;

fullader uut(x,y,cin,sum,cout);

initial begin

$dumpfile("fullader_tb.vcd");

$dumpvars(0,fullader_tb);

x=0; y=0; cin=0;

#5 x=0; y=0; cin=1;

#5 x=0; y=1; cin=0;

#5 x=0; y=1; cin=1;

#5 x=1; y=0; cin=0;

#5 x=1; y=0; cin=1;

#5 x=1; y=1; cin=0;

#5 x=1; y=1; cin=1;

end

initial begin

$monitor("t=%3d,\tx=%d,\ty=%d,\tcin=%d,\tsum=%d,\tcout=%d\n",$time,x,y,cin,sum,cout);

end

endmodule

Result:

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